As IC components have continued to decrease in size, improvements to scale have spawned design implementation issues for some types of features, e.g., in CMOS ICs with features sized less than approximately twenty-two nanometers (nm). As IC technology continues to shrink, the growing need for empirical data from a design may exacerbate the uncertainty of the manufacturing process, thereby increasing the risk of defects or impaired operability. Conventional approaches for traversing physical limits may apply manual or computer-implemented techniques for increasing the resolution of chips printed using optical lithography. One such technique is known as optical proximity correction (OPC). OPC is a computational method for correcting irregularities and distortions arising from diffraction effects by the transforming of mask geometries.
Conventional OPC approaches can use empirical approximation models to predict the effect of imaging errors on the printing of an IC due to manufacturing constraints, diffraction effects, etc. Such models can receive an input in the form of multiple patterns each representative of an ideally printed feature. Using this input, a model can be generated to show expanded and corrected formats of the patterns, known as shapes, which account for possible manufacturing and printing errors. The OPC model can then be used as a basis for printing the product. An OPC model can therefore include one or more feature shapes which may have an associated “printability metric,” a measurement for determining how each pattern affects the ability to fabricate the IC from the design layout. Two example printability metrics can include: Lithographic Difficulty Estimators (LDE) and the critical dimension. An “LDE,” as used herein, can refer to a multiplying coefficient calculated for a particular group of patterns, which represents process-related factors which can decrease the printability metric of each pattern in a given region. The LDE can be directly proportional to the critical dimension for two features in a region. A “critical dimension” refers to the smallest distance between two features of a particular region, below which the features cannot be reliably printed to a wafer or mask. Regions with lower value LDEs and/or higher critical dimensions relative to others generally reflect a higher level of printability.
Conventional techniques may address one or more concerns relative to technology scaling and the ever-decreasing separation distance between features in an IC layout. Traditional OPC adjustment mechanisms may include, e.g., modifying a selected feature which may be difficult to print due to the physical proximity and associated effects of one or more neighboring features in a region of printed feature patterns within the IC layout. In some cases, a particular feature may cause or contribute to an unusually low printability metric for one or more of its neighboring features in an IC layout. Such effects on the printability metric of individual features in a design layout have become more pronounced with further reductions in feature size. Techniques for reconfiguring or resizing features in an IC layout will continue to affect the quality of a product as the size of each feature, and the separation distance between neighboring features, in an IC layout continues to decrease.